Verification of Chisel Hardware Designs with ChiselVerify

With the current ever-increasing demand for performance, hardware developers find themselves turning ever-more towards construction of application-specific accelerators to achieve higher performance and lower energy consumption. In order meet ever-shortening time constraints, both development verification tools need be improved. Chisel, as a language, tackles this problem by speeding up digital designs. However, Chisel infrastructure lacks verification. This paper improves efficiency in proposing methods support formal dynamic designs Scala. It builds on top ChiselTest, official testing framework Chisel. Our work supports functional coverage, constrained random verification, bus models, transaction-level modeling library named ChiselVerify, while are directly integrated into Chisel3.